SerDes Digital Design Lead Speed IP Architect
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-11-05
Listing for:
Eliyan
Full Time
position Listed on 2026-11-05
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading chiplet startup is seeking a Ser Des Digital Design Lead to drive architecture and implementation of high-speed serial link IPs targeting 224G and 448G data rates. You will work on digital logic for cutting-edge interconnect products within a collaborative, innovative environment. The ideal candidate has over 12 years of experience in digital design, a Master's or Ph.D. in Electrical Engineering, and strong RTL design skills.
This role offers a great work environment and excellent benefits.
The Ser Des Digital Design Lead
- High-Speed IP Architect position in the Marketing & Media field is open for applications. We aim to respond to suitable candidates as soon as possible. Full responsibilities and requirements are described in the listing above. Learn more about the Ser Des Digital Design Lead
- High-Speed IP Architect role in the description above.
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