Autonomous Physical Design Lead; Tapeout
Listed on 2026-11-05
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Research/Development
Electronics Engineer
Phinity Labs, an AI research lab in San Francisco, seeks a Physical Design Lead to drive block-to-full-chip PD flows and optimize PPA. You will define synthesis-to-layout flows, PDN, clock trees, and cell characterizations, delivering tapeout-ready designs.
You will collaborate with top researchers and hardware experts, shape strategy, and own high-impact PD initiatives across power, performance, and area trade-offs in cutting-edge accelerator chips.
Step into the Autonomous Physical Design Lead (Tapeout Ready) role at Phinity Labs in San Francisco, CA, United States and grow with us.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Autonomous Physical Design Lead (Tapeout Ready) role in the description above.
We appreciate your interest in this position.
Join Phinity Labs and contribute to our ongoing work.
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