Senior SoC Lead: Chiplet Architect & Tapeout Leader
Listed on 2026-10-11
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Design & Architecture
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IT/Tech
Hardware Engineer
Lattice Semiconductor is seeking a Senior SoC Chip Lead for our San Jose office. You will own chip tapeout, drive architecture decisions, and lead cross-functional teams across multiple sites to accelerate development of next-generation SoCs.
Qualifications include 20+ years in FPGA/SoC design, expert System Verilog and SSTA skills, and a proven track record of delivering tapeouts. This role emphasizes leadership, architecture influence, and strategic roadmap planning.
This position is for the Senior SoC Lead:
Chiplet Architect & Tapeout Leader role at Lattice Semiconductor.
This is an excellent position to take on the Senior SoC Lead:
Chiplet Architect & Tapeout Leader role at Lattice Semiconductor.
As a Senior SoC Lead:
Chiplet Architect & Tapeout Leader, you will play an important part at Lattice Semiconductor in San Jose, CA, United States.
We invite applications for the Senior SoC Lead:
Chiplet Architect & Tapeout Leader position located in San Jose, CA, United States.
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