VP, SerDes Validation

Position: VP, SerDes Validation and Applications
Altera  .#
** Job Details:**### ##
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* Job Description:

** Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. As a standalone business unit spun out from Intel’s Programmable Solutions Group, Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.### ###
** Position Overview
** We are seeking a visionary and technically accomplished Vice President to lead our Ser Des Validation and Applications Engineering organization. This role is critical to ensuring the robustness, performance, and customer success of Altera’s high-speed serial interface technologies across our FPGA product portfolio.### ###
** Key Responsibilities**
* ** Strategic Leadership**  + Define and execute the validation and applications strategy for Ser Des IP across Altera’s product lines.  + Lead cross-functional initiatives to ensure first-time silicon success and customer satisfaction.  + Represent Altera in industry standards bodies and technical forums related to Ser Des technologies.
* ** Technical Oversight**  + Oversee post-silicon validation, electrical characterization, and compliance testing of Ser Des interfaces (e.g., PCIe, Ethernet, JESD, SATA).  + Drive development of automated test platforms and regression suites for Ser Des validation.  + Ensure robust system-level validation and debug methodologies are in place.
* ** Team Management**  + Build and mentor a high-performing team of validation and applications engineers.  + Foster a culture of innovation, collaboration, and continuous improvement.  + Plan and manage capital equipment and resource allocation for validation labs.
* ** Customer Engagement**  + Provide technical support and guidance to strategic customers during product bring-up and deployment.  + Collaborate with sales and field engineering teams to resolve customer issues and gather feedback for future product improvements.### ##
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* Qualifications:

*** Master’s or PhD in Electrical Engineering, Computer Engineering, or related field.
* 15+ years of experience in semiconductor validation, with deep expertise in Ser Des technologies.
* Proven leadership experience managing large, cross-functional engineering teams.
* Strong understanding of high-speed serial protocols and signal integrity challenges.
* Experience with lab equipment (oscilloscopes, BERTs, VNAs), scripting (Python, Tcl), and FPGA tools (Quartus, Vivado).
* Excellent communication, strategic thinking, and problem-solving skills.### ##
** Job Type:
** Regular### ##
** Shift:
** Shift 1 (United States of America)### ##
** Primary

Location:

** San Jose, California, United States### ##
** Additional Locations:**### ##
** Posting Statement:
** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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