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Formal Verification Engineer
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2025-12-01
Listing for:
ACL Digital
Full Time
position Listed on 2025-12-01
Job specializations:
-
Engineering
Electronics Engineer, Software Engineer, Test Engineer
Job Description & How to Apply Below
Overview
Looking for an experienced formal verification engineer with hands-on experience on development of FPV, DPV, AEP & SEQ setups and system Verilog assertion expertise.
Responsibilities- Develop formal verification setup using System Verilog modules and Assertions
- Run formal verification checks, analyze the results, and debug any issues
- Develop and enhance constraints, checks, and cover points to achieve verification quality
- Analyze and deploy formal convergence techniques like abstraction, black boxing and design reductions
- Must have experience in Formal Verification (Min 3+ years)
- Associate
- Contract
- Industries:
Semiconductor Manufacturing
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