Staff Engineer, PCB Layout

Location: San Jose, CA, US

The Staff Engineer, PCB Layout works with cross functional teams with other PCB Layout designers, customers, manufacturing engineering and project leadership to ensure robust and high quality product development. Enhance designs with feedback from reviews in areas such as manufacturing, test, supply chain, reliability, industrial design and simulations. Provide support throughout the manufacturing process of the electrical/mechanical system that they have designed.

Performs tasks such as, but not limited to, the following:

Spearhead the design, development, and implementation of technical solutions for complex, multi-domain projects. This includes developing deployment strategies and plans.

Act as a recognized expert, offering technical leadership and direction to a sizable team of engineers. You will also analyze complex systems and recommend solutions.

Review and interpret customer requirements and specifications, and potentially serve as the primary customer contact. You may also manage relationships with key vendors.

Research new system ideas, create design plans, and modify existing systems to meet both customer and Celestica's needs. You will also solve complex problems and create designs that adhere to all relevant procedures and standards.

Create, modify, and improve PCB designs and techniques using Computer-aided Design (CAD) software.

Actively participate in project planning, scheduling, and design reviews. You will provide feedback and support to other engineering functions from the initial design phase through manufacturing to resolve any issues.

Keep up-to-date with relevant industry knowledge and regulations to ensure all designs and processes remain compliant.

• PCB Design Expertise:
  Expert in Cadence Allegro (versions 16.x & 17.x) and experienced with high-density PCBs (up to 28 layers) and high-speed layout design. Experience with Valor Trilogy 5000/NPI is a plus.
• Technical Knowledge:
  Strong knowledge of PCB & PCBA manufacturing processes, industry and quality standards (including IPC), Signal Integrity, EMC, and EMI layout requirements.
• Experience in high-speed digital hardware design and development, with an understanding of architecture, reliability, prototyping, and failure analysis. Specific experience with DDR5, 100
  
  GbE, PCIe Gen5, and 56G SERDES is highly valued.
• Strong engineering design experience in Compute, Storage, or Network products. Knowledge of AI products, GPU servers, and high-speed OSFP/QSFP networking design is a significant plus.
• Possesses strong organizational, planning, and program management skills. The ability to work collaboratively in a team to meet aggressive deadlines and quality standards is required.
• A self-motivated individual capable of working in a dynamic environment with complex design requirements. Also has strong knowledge of IT platforms and database design.

• Duties of this position are performed in a normal office environment.
• Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data.
• Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required.
• Occasional travel may be required.

• 7 to 10 years of related experience;
  Experience in similar job roles

Bachelor degree or consideration of an equivalent combination of education and experience.

The salary range described in this posting is an estimate by the Company, and may change based on several factors, including not limited to a change in the duties covered by the job posting, or the credentials, experience or geographic jurisdiction of the successful candidate. Salary Range: $128K-200K Annually

This job description is not intended to be an exhaustive list of all duties and responsibilities of the position. Employees are held accountable for all duties of the job. Job duties and the % of time identified for any function are subject to change at any time.

All qualified applicants will receive…