Lead Analog IC Designer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The lead Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

• Candidate’s background should include a minimum of 3 years of experience in CMOS Ser Des or high-speed I/O IC design and development
• Working knowledge of a set of common Ser Des standards and their electrical requirements is a plus
• Proficient design experience in most of the following Ser Des circuit blocks:
  Driver;
  Receiver;
  Serializer;
  Deserializer;
  Phase Interpolator; PLL;
  High Speed Clock Distribution; ADC and DAC;
  Bias and Bandgap; and Voltage Regulators
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
• Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification
• Cadence tool experience, lab test experience, and design experience at >112
  
  Gbps and in
• MS or PhD in EE

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.