Physical Verification Engineer

This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

This is a unique opportunity to be at the forefront of AMD’s next‑generation product development. In this role, you will drive design verification flows that enable robust product design and successful tapeout, including advanced silicon technologies and 3

DIC packaging solutions.

We are seeking a highly skilled Physical Verification Engineer to join our team. The candidate will be responsible for developing and maintaining Design Rule Check (DRC) decks, supporting product‑level physical verification sign‑off, and ensuring compliance with manufacturing requirements through Design for Manufacturability (DFM) flows.

• Develop, validate, and maintain DRC decks for advanced technology nodes
• Support product and IP physical verification sign‑off, including:
• Performing QA on physical verification flows
• Reviewing and approving waiver requests
• Collaborating with design teams to resolve violations
• Work closely with foundry and internal teams to ensure rule compliance and process alignment
• Implement and optimize DFM flows to improve yield and manufacturability

• Strong experience in physical verification tools (e.g., Mentor Calibre, Synopsys IC Validator).
• Proficiency in SVRF, TVF, or similar rule deck languages
• Familiarity with advanced process nodes (TSMC 2nm & 3nm) and foundry design rules
• Knowledge of DFM methodologies and best practices
• Working experience of LVS, RC Extraction, EMIR and PERC ESD flow is preferred
• Prior experience in supporting semiconductor product sign‑off is preferred
• Excellent problem‑solving and communication skills

• Bachelor degree in engineering or physical science, preferably with advanced degree (MS or PhD)

San Jose, CA

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.