Staff Engineer, Serdes Analog Design
Listed on 2025-12-20
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Engineering
Electrical Engineering, Systems Engineer, Electronics Engineer
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Advancing the World’s Technology TogetherOur technology solutions power the tools you use everyday--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.
Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy. What You’ll DoIn this role, you will actively work on architecture and circuits of high-speed interconnect transceiver (Serdes). You will work on circuits for Serdes IPs, clock generation as well as traditional analog circuits and develop high-performance and low‑power serdes including display interface, camera sensor interface, UCIe / die‑to‑die interconnect and 224/448
Gbps UA‑link/Ethernet using cutting‑edge process technologies.
- Design low‑power and low‑voltage analog and custom digital circuit components using advanced CMOS process technologies
- Translate component design specification to schematics. Build simulation test‑benches to evaluate circuit performance, functionality, power consumption and reliability.
- Supervise layout designers to generate LVS/DRC clean layout. Optimize layout to improve power consumption and performance of circuits.
- Functionality and performance validation in Silicon.
- Bachelors with 10+ years, Masters with 8+ years or PhDs with 5+ years of experience.
- Knowledge and experience with analog circuits/mixed signal circuits: such as bandgap, LDO, filters.
- Knowledge and experience with circuits of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
- Knowledge of Serdes architecture and high‑speed interconnect standard (USB, PCIe, UCIe).
- Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.
- Well‑versed in EDA tools (Cadence, Spectre, Totem, EMX).
- Comfortable with scripting languages (Python, Matlab).
- You’re inclusive, adapting your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change.
The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones.
In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.
- Give Back:
With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. - Enjoy Time Away: 4+ weeks of paid time off a year, plus holidays and sick leave.
- Care for Family:
Stipend for fertility…
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