Principal Engineer, Platform Systems Architect - Rack Design

Principal Engineer, Platform Systems Architect – Rack Design

We are looking for a Principal Engineer, Platform Systems Architect – Rack Design to join Ayar Labs.

Location: San Jose (on-site)

The successful candidate will collaborate with customers and interface with internal teams (laser, mixed‑signal silicon, photonics, packaging) to design AI rack platforms using Ayar Labs’ CPO silicon photonics optical engines and ELSFP modules. The candidate will translate customer system requirements into AI rack physical specifications and collaborate with design teams to ensure spec compliance.

The candidate will represent Ayar Labs at standard‑setting organizations (SSOs) and promote Ayar Labs’ optical interconnect technology. The candidate will collaborate with the CTO office on path‑finding activities, product and technology roadmaps.

• Use Ayar Labs’ in‑package optical I/O as the foundational technology, work with customers to design AI rack platforms for scale‑up and scale‑out fabrics and extended memory.
• Formulate AI rack platform specifications based on customer system requirements and collaborate with design teams to ensure spec compliance for the rack systems.
• Work on path‑finding activities and advanced product & technology roadmaps.
• Participate on SSOs such as Open Compute, UEC, ESUN, Ultra Accelerator Link, OIF, and IEEE 802.3.
• Participate in technology evangelization through customer presentations, conference papers, seminar/webinars.

• MS degree in Mechanical or Electrical Engineering or equivalent
• 10+ years of industry experience
• 5+ years of experience in AI/ML, HPC and networking platforms
• AI or HPC compute chassis and rack design experience
• Experience with thermal analysis, air‑cooled or liquid cooling solutions, interconnect cabling, fiber management, rack physical design, chip packaging, power delivery, signal integrity
• Understanding of OAM, OSFP/QSFP, and PCIe cards and connector specifications
• Understanding of NRZ, PAM4, and coherent modulations
• Understanding of D2D and Ser Des links
• Familiar with relevant standard‑setting standards
• Experience with AutoCAD, Shapr3D, or similar

• Ph.D.
• Optical interconnect experience

Salary range: $180,000 - $240,000

Note: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.

Ayar Labs is an affirmative action/equal opportunity employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship.

Veterans are more than welcome and encouraged to apply.