Substrate​/Advanced Package Engineer

Substrate / Advanced Package Engineer (7103) Context

As chip sizes increase and packaging technologies become more complex, substrate engineering is emerging as a critical domain. This role supports TSMC’s leadership in 3

DIC and advanced packaging by extending expertise beyond chip-level design into package-level integration. The team is addressing challenges such as warpage, power delivery, thermal management, and material innovation. Future evolution includes Chip-on-Wafer-on-PCB (CoWoP) under TSMC’s System Technology Optimization program.

The position requires strong design and technology expertise to define future customer requirements, focusing on integrated packaging (IP), dielectric parameters, high-speed I/O, and trade-offs that directly impact system performance. This role is critical in shaping the direction of 3

DIC development.

We are seeking a highly skilled and motivated Substrate / Advanced Package Engineer to join our cutting‑edge 3

DIC design team. The ideal candidate will have a strong foundation in semiconductor physics, mechanical engineering principles, and EDA tools, with a passion for innovation in advanced package design. The role involves design, simulation, and modeling of complex substrate and packaging technologies to support next generation 3

DIC applications.

• Design, simulate, and optimize advanced packaging for 3
  
  DIC applications.
• Collaborate with cross‑functional teams to define specifications and requirements.
• Perform modeling of warpage, stress, reliability, and thermal performance using industry‑standard EDA tools.
• Formulate and solve problems in research‑driven, often ambiguous domains.
• Provide guidance on high‑speed I/O modeling and integration.
• Develop and maintain documentation, including specifications, test plans, and design reviews.
  Stay current with industry trends, tools, and technologies in advanced packaging.

• Master’s degree or Ph.D. in Electrical Engineering, Mechanical Engineering, or a related field.
• 15+ years of hands‑on expertise in advanced packaging technologies and substrate design.
• Understanding of semiconductor device physics and packaging process technologies.
• Strong knowledge of warpage, stress, and thermal effects in packaging.
• Proven ability to drive solutions in ambiguous, research‑oriented contexts.
• Excellent problem‑solving, analytical, and communication skills.
• Strong collaboration skills, with the ability to mentor junior engineers.
• Ability to balance strategic insight with hands‑on technical execution.

• Experience with reliability, IR/EM, and multi‑physics analysis.
• Familiarity with machine learning techniques for design optimization.
• Patents, publications, or demonstrated innovation in substrate or packaging domains.

• Ability to provide impactful, data‑driven suggestions that influence design direction.
• Effective use of modeling and simulation to validate proposals.
• Establishing trust and credibility with global teams.
• Enabling adoption of new technologies within the 3
  
  DIC ecosystem.

• San Jose, CA or Hsinchu, Taiwan.

At TSMC, you will be part of the world’s leading semiconductor foundry, driving cutting‑edge innovation in advanced packaging and 3

DIC technologies. You will collaborate with world‑class engineers, work on industry‑defining projects, and shape the future of system integration. We offer unparalleled opportunities for growth, impact, and contribution to the global technology ecosystem.

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology

TSMC pioneered the pure‑play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor…