Lead DFT Design Engineer SoC/ASIC
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-01-01
Listing for:
Cadence Design Systems
Full Time
position Listed on 2026-01-01
Job specializations:
-
Engineering
Electronics Engineer, Engineering Design & Technologists -
IT/Tech
Engineering Design & Technologists
Job Description & How to Apply Below
A leading electronic design automation company in California seeks an experienced SoC/ASIC Digital Design Engineer with a strong focus on Design for Test (DFT) methodologies. The ideal candidate will have substantial expertise in scan chain insertion, compression scan technologies, and automatic test pattern generation (ATPG), along with strong problem-solving skills and the ability to work collaboratively in a cross-functional team environment.
This is a fantastic opportunity to contribute to essential technology projects.
#JLjbffr
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×