Senior DFT Design Engineer

Overview

We are seeking a senior skilled DFT Design Engineer to develop and implement comprehensive Design for Test solutions across our semiconductor products. This role involves RTL design, verification, and manufacturing support for various DFx methodologies including SCAN, MBIST, and BSCAN implementations. We are seeking a highly skilled DFT Design Engineer to join our semiconductor engineering team and drive the development of cutting-edge Design for Test solutions across our product portfolio.

This critical role combines deep technical expertise in digital design with specialized knowledge of test methodologies to ensure our silicon products meet the highest quality standards for high-volume manufacturing.

As a Senior DFT Design Engineer, you will be responsible for architecting, implementing, and optimizing comprehensive test strategies that span from initial RTL development through production manufacturing. You will work at the intersection of design and test, collaborating with cross-functional teams including architecture, verification, physical design, and manufacturing to deliver robust DFT solutions that enable efficient testing while meeting stringent power, performance, and area requirements.

The successful candidate will have extensive experience in DFT methodologies and will play a pivotal role in defining test architectures for complex SoCs, developing innovative solutions to challenging testability problems, and ensuring seamless integration of DFT features across multiple design hierarchies.

This position offers the opportunity to work on industry-leading semiconductor products and contribute to the advancement of DFT technologies in next-generation computing platforms. This role involves RTL design, verification, and manufacturing support for various DFx methodologies including SCAN, MBIST, and BSCAN implementations, with a focus on achieving optimal test coverage, minimizing defect escape rates, and reducing overall test costs while maintaining design integrity and performance targets.

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