More jobs:
Senior Mixed-Signal Model Verifier; SystemVerilog/Co-Sim
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-01-01
Listing for:
Dexian DISYS
Full Time
position Listed on 2026-01-01
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading staffing and technology firm in San Jose is looking for a Mixed Signal Model Verification Engineer. This hybrid role involves verifying System Verilog models against custom circuit schematics utilizing formal equivalence checking and co-simulation. Ideal candidates have extensive experience in System Verilog, co-simulation, and a strong background in analog integrated circuits. They offer competitive pay of $90-$95 per hour for this position.
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Position Requirements
10+ Years
work experience
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