Principal Engineer, ASIC Design Verification

Location: San Jose, CA

Job : 500

# of Openings: 0

Location:

San Jose (on-site)
We are seeking a Principal Design Verification Engineer to lead the verification strategy for our next-generation silicon photonic chip. In this role, you will serve as a technical lead, architecting scalable verification environments and driving high-quality silicon from concept to tape-out. You will look beyond block-level testing to solve complex system-level challenges, define methodologies, and mentor a growing team of bright engineers.

Essential Functions:

• Architect Test benches:
  Define and build modular, reusable, and scalable UVM testbench architectures for complex IP blocks and sub-systems.
• Drive Methodology:
  Set the standard for verification methodologies, coding guidelines, and coverage metrics. Evaluate and deploy new EDA tools, formal verification techniques, or emulation flows.
• Strategic Planning:
  Collaborate with architects and RTL designers early in the cycle to define the verification plan, identify architectural bottlenecks, and ensure micro-architecture testability.
• Complex Debugging:
  Lead the effort to debug elusive hardware bugs, root-causing issues across RTL, firmware, and the verification environment.
• Technical Leadership:
  Mentor senior and junior engineers, conduct code reviews, and foster a culture of engineering excellence.
• Automation & Efficiency:
  Develop scripts and infrastructure to automate regression testing, performance analysis, and coverage closure.

Basic Qualifications:

• MS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience in ASIC/SoC verification.
• Expert-level proficiency in System Verilog and UVM (Universal Verification Methodology).
• Proven track record of building verification environments from scratch (agents, scoreboards, sequencers, etc.).
• Deep knowledge of standard interface protocols (PCIe, ARM MCU, AMBA/AXI, UCIe).
• Strong proficiency in scripting languages for automation (Python, Perl, Tcl, or Shell).
• Experience defining functional coverage groups and driving logic verification to 100% closure.

Preferred Qualifications:

• Experience with formal property checking (VC Formal) and writing SVA (System Verilog Assertions).
• Hands-on experience with hardware emulation platforms.
• Familiarity with RISC-V or ARM architecture and coherency protocols.
• Experience in Analog/Mixed-Signal (AMS) verification.
• Experience with C/C++ or System
  
  C modeling for reference models.
• Experience working on digital designs with multiple clock domains and clock dividers.
• Experience in verification of Ser Des IP block interfaces in a complex SoC fabric environment.
• Experience in verification of the PCS, PMA Ser Des layers and internal Ser Des digital backends.
• Experience with verification of HBM memory interfaces (PHY and controller).
• Experience with formal model equivalence checking tools and verification methodology.
• Programming experience in Python.

Salary range: $180,000 - $230,000

NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.

About Ayar Labs:

At Ayar Labs we’re about to revolutionize computing by moving data with light. We’re unleashing processing power for artificial intelligence, high performance computing, cloud and telecommunications by removing the bottlenecks created by today’s electrical I/O – making it possible to continue scaling computing system performance. Ayar Labs is the first to deliver an optical I/O solution that combines in-package optical I/O chiplets and multi-wavelength remote light sources to replace traditional electrical I/O.

This silicon photonics-based I/O solution enables chips to communicate with each other from millimeters to kilometers, to deliver orders of magnitude improvements in latency, bandwidth density, and power consumption.

With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and…