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Senior Memory IP Engineer — Post-Silicon & Debug Lead

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Cadence Design Systems, Inc.
Full Time position
Listed on 2026-01-03
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading electronic design automation company in San Jose is seeking a Post Silicon Memory Product Engineer to support the integration of advanced memory IP solutions. The role requires 7+ years of experience in Electrical/Computer Engineering, with strong skills in debugging and collaboration. You will be integral in ensuring the successful deployment of Memory PHY and Controller IP, and you will work closely with top technology firms.

This position offers competitive compensation and opportunities for career growth.
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Position Requirements
10+ Years work experience
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