Senior ASIC​/SoC Design Verification Engineer

A technology company is seeking a Design Verification Engineer to ensure functional correctness of ASIC/SoC designs in a datacenter AI environment. The role involves developing verification plans, executing test cases, and debugging with RTL designers. Candidates should have a BS/MS in Electrical Engineering or relevant field and experience with System Verilog and UVM. This is a contract position offering competitive compensation between $150,000 and $250,000 annually.
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