PCIe Protocol Engineer; Tech Staff Engineer

The Candidate will be an expert with 32

Gbps SERDES (Serializer/Deserializaer) based protocols, and must possess recent work experience with PCIe Rev.
3, 4 and 5 protocol

Minimum Qualifications:

1. BSEE / BSCS with 10+ years of experience.
2. Knowledge of FPGA architectures is a must
3. Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios
4. Strong technical background in FPGA prototype emulation, and debug
5. Strong technical background in silicon validation, failure analysis and debug
6. Excellent Board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal)
7. Design with RTL coding in Verilog and VHDL is a must
8. Experience using Simulation (Model Sim) and Synthesis (Synplicity) tools
9. Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB
10. Familiarity with the bring up and on-board debug of 32

Gbps SERDES
11. Hands-on systems level design and debug experience with following high-speed serial communications protocols (must: PHY, PCS and Data link layer of the OSI protocol stack; desirable: transaction and upper layers of the OSI protocol):
a. PCIe Gen3/4/5
12.

Experience with the PCI-SIG Compliance Tests
a. Protocol Testing
b. PCI-CV Testing
c. PHY Testing
13.

Experience with the PCIe Lab Equipment
a. PCIe Analyzer
b. PCIe Exerciser
14. Strong commitment to quality and customer satisfaction
15. Excellent verbal and written communication skills in English
16. Able to travel 0-2 times annually if required.

Preferred qualifications:

1. Familiarity with any high speed SERDES controllers that make use of 32

Gbps PCS, PMA :
a. Ethernet 1, 2.5, 5, 10, 25, 40, 50, 100, 200, 400 Gbps, including familiarity with (U)
S(X)
GMII
b. Interlaken (4.25 to 412.5 Gbps)
c. OTN OTUx (2.66 to 131 Gbps), or SONET/SDH OC3/12/48/192
d. (E,X,XGS,NG)-PON or 100G-EPON
e. Video interfaces SDI-SD/HD/3

GHD and SDI (5.94, 11.88

Gbps), Displayport (6.48 to 25.92

Gbps), HDMI (3.96 to 42.66 Gbps)
f. JESD
204C (6.375 to 32 Gbps)

2. Design and debug experience for any of the below high-speed serial communications protocols is a plus, but not necessary:
a. Hybrid Memory Cube
b. CPRI Rate 1 to 10+
c. Serial Rapid IO 4.1
d. Firewire
e. Litefast
f. USB 3.0
g. SATA I, II, III
h. Fiber Channel
i. Coa Xpress

3. C, C++ or object-oriented programming skills is desirable
4. Knowledge and experience in embedded firmware development is desirable
5. Good understanding of embedded firmware/software development process is desirable
6. Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable
7. Knowledge of PERL/TCL scripting is desirable