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ASIC Verification Engineer — SystemVerilog​/UVM Specialist

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: SQL Pager LLC
Full Time position
Listed on 2026-01-07
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 130000 USD Yearly USD 100000.00 130000.00 YEAR
Job Description & How to Apply Below
A leading company in semiconductor technology is seeking a VLSI Verification Engineer who will collaborate with design teams and develop verification environments. The ideal candidate has a strong background in ASIC/FPGA verification, advanced knowledge of System Verilog, and is skilled in both C/C++ and scripting languages.

This role offers diverse challenges and opportunities to work on cutting-edge technology in a collaborative environment.
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