More jobs:
Senior DFT Design Architect SoC/ASIC
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-01-07
Listing for:
Cadence Design Systems, Inc.
Full Time
position Listed on 2026-01-07
Job specializations:
-
Engineering
Engineering Design & Technologists -
IT/Tech
Engineering Design & Technologists
Job Description & How to Apply Below
A leading technology firm is seeking an experienced SoC/ASIC Digital Design Engineer in San Jose, California. The candidate will focus on Design for Test (DFT), requiring experience in scan chain insertion, compression scan technologies, and Automatic Test Pattern Generation (ATPG). Ideal candidates will demonstrate strong problem-solving skills and collaboration with cross-functional teams. This role encourages independent task completion and values US citizenship.
A calculated method and discipline in addressing challenges are key for success in this fast-paced environment.
#JLjbffr
Position Requirements
10+ Years
work experience
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×