Senior Staff Engineer, GPU Design Verification; Subsystems

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world.

Come build with us!

As a Senior Staff GPU Design Verification Engineer – Subsystems, you will help shape the verification of one or more GPU subsystems for Samsung’s next-generation mobile GPU. In this high-impact individual contributor role, you will contribute to the verification strategy and hands-on validation of complex subsystem designs, ensuring functional correctness, performance integrity, and architectural intent. You bring strong expertise in GPU design verification, strong block- and subsystem-level architectural understanding, and a collaborative leadership style that aligns architecture, design, and software teams while supporting concurrent development cycles.

Leveraging your expertise in one or more technical areas, you will contribute to the verification strategy and execution for one or more GPU subsystems by developing comprehensive verification plans, defining verification goals, coverage metrics, and sign-off criteria aligned with architectural specifications and integration requirements. You excel at architecting and implementing advanced verification environments. You design, develop, and maintain scalable verification test benches using System Verilog, UVM, and C++, developing test code in parallel with RTL and applying constrained-random testing, coverage-driven verification, and assertion-based techniques to validate complex block and subsystem behaviors.

You ensure functional and performance excellence across subsystem coverage by helping advance verification methodologies, tools, and automation to improve efficiency and quality, while creating targeted and scalable test scenarios that stress interactions across multiple blocks, interfaces, and data paths within the subsystem. You help drive complex debug and issue resolution by analyzing failures spanning blocks within a subsystem, identifying root causes, and collaborating with design and architecture teams to ensure verification aligns with architectural intent and system-level integration expectations.

You inspire high performance by mentoring engineers, exemplifying a culture of ownership and innovation, and staying ahead of emerging verification technologies and methodologies.

• 10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a Ph.D.
• 8+ years of hands‑on experience in GPU, CPU, or advanced semiconductor design verification.
• Strong understanding of computer architecture and GPU subsystem design, including block‑level and subsystem‑level integration.
• Strong programming skills in C/C++, Python, Perl, or equivalent.
• Strong expertise in System Verilog and UVM, including constrained‑random testing, functional coverage, and assertions.
• Experience with building configurable UVM test benches for reuse across design hierarchies, ensuring a block‑level environment can seamlessly transition into a system‑level environment.
• Proven track record of achieving multiple first‑pass silicon success.
• Experience with contributing to verification strategy and execution for multiple subsystem blocks and verification closure across interfaces.
• Excellent debugging, analytical, and…