Senior HSIO Architect: PCIe/UCIe & SerDes Lead
Listed on 2026-10-07
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Engineering
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Design & Architecture
Tyl Semi in San Jose is seeking a High-Speed IO Architect to lead the architecture of high-speed interfaces across product families. You will drive key decisions on Ser Des architecture and UCIe integrations while collaborating with engineering teams and vendor partners.
The ideal candidate has over 15 years of experience, including significant expertise in PCIe and UCIe standards, alongside a strong track record in managing complex IP integrations.
Our team is growing, and we are hiring a Senior HSIO Architect: PCIe/UCIe & Ser Des Lead in San Jose, CA, United States.
We are looking to fill the Senior HSIO Architect: PCIe/UCIe & Ser Des Lead position at Tyl Semi in San Jose, CA, United States.
The Senior HSIO Architect: PCIe/UCIe & Ser Des Lead role at Tyl Semi is now open for applications in San Jose, CA, United States.
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