MTS Validation Engineer — DDRMemory & Debug; Hybrid
Listed on 2026-10-07
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Engineering
Systems Engineer, Test Engineer, Electronics Engineer, Validation Engineer
Rambus, a leader in memory interface chips, seeks an experienced applications engineer with DRAM and failure analysis expertise to support international customers in Korea and across Asia. Analyze and debug complex issues involving DRAM, DIMMs, servers and BIOS interactions.
Responsibilities include validating new chip designs, assisting with DDR5 server memory interface validation, collecting signal integrity data, and preparing failure analyses and reports.
We are seeking a motivated MTS Validation Engineer — DDR5 Memory & Debug (Hybrid) to join in San Jose, CA, United States.
Consider building your career as a MTS Validation Engineer — DDR5 Memory & Debug (Hybrid) at
The MTS Validation Engineer — DDR5 Memory & Debug (Hybrid) position in the Engineering field is open for applications.
We have an opening for a MTS Validation Engineer — DDR5 Memory & Debug (Hybrid) in San Jose, CA, United States within Engineering.
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