Lead ASIC Verification Engineer - SystemVerilog​/UVM

Broadcom is seeking an experienced verification lead to architect and implement scalable testbench environments for Block/Core/SOC verification in a high‑level ASIC flow. You will drive verification plans, create pseudo‑random test strategies, and close coverage gaps while mentoring junior engineers.

You should have extensive System Verilog/UVM experience, strong debug skills, and familiarity with PCIe or similar protocols. This role is based in San Jose, CA, with a competitive benefit package.

For the Lead ASIC Verification Engineer
- System Verilog/UVM position at Broadcom, we are reviewing applications now.

We are looking to fill the Lead ASIC Verification Engineer
- System Verilog/UVM position at Broadcom in San Jose, CA, United States.

The Lead ASIC Verification Engineer
- System Verilog/UVM role at Broadcom is now open for applications in San Jose, CA, United States.

Join us at Broadcom as our next Lead ASIC Verification Engineer
- System Verilog/UVM in San Jose, CA, United States.