Analog Intern: PMIC Architecture & Cadence Design
Listed on 2026-10-10
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Engineering
Electronics Engineer, Engineering Design & Technologists -
Design & Architecture
Engineering Design & Technologists
Renesas Electronics is seeking a Summer 2027 Analog Intern to assist the Memory Interface Division in developing the next generation DDR PMIC. The intern will research PMIC control architectures, with DE/AE support, and will perform simulations at multiple levels while building circuits in Cadence.
Preferred candidates are current PhD or Master students who are self-driven, with a strong background in Power Electronics and Analog design, and familiarity with SIMPLIS and Cadence.
Consider building your career as a Analog Intern: PMIC Architecture & Cadence Design at Renesaselectronics.
We would love to welcome a new Analog Intern: PMIC Architecture & Cadence Design to our group in San Jose, CA, United States.
For the Analog Intern: PMIC Architecture & Cadence Design position at Renesaselectronics, we are reviewing applications now.
Step into the Analog Intern: PMIC Architecture & Cadence Design role at Renesaselectronics in San Jose, CA, United States and grow with us.
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