Senior STA Engineer — Timing Closure & Synthesis Expert
Listed on 2026-10-11
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Engineering
Quality Engineering, Electronics Engineer
Quest Global is seeking an STA engineer in San Jose, CA to lead timing closure across chip topologies. The role focuses on ensuring robust performance through full-chip and block-level analysis, with emphasis on timing budgets and signoff readiness.
You will debug timing issues, perform synthesis, equivalence checking and STA using Synopsys tools in a fast-paced environment supporting Fortune 500 clients.
Step into the Senior STA Engineer — Timing Closure & Synthesis Expert role at Quest Global in San Jose, CA, United States and grow with us.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior STA Engineer — Timing Closure & Synthesis Expert role in the description above.
We appreciate your interest in this position.
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