Senior Principal SI/PI Engineer Speed IP Debug
Listed on 2026-10-13
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Engineering
Systems Engineer, Electronics Engineer, Test Engineer, Quality Engineering
Cadence Design Systems is seeking a Sr Principal SI/PI Engineer to join the HPP IP R&D Group. This hands-on role focuses on high-speed IP products, SI/PI optimization, and collaboration with chip designers.
You will work on test chip package design, evaluation board optimization, and provide channel models. Requires MS/PhD in EE, 3+ years Ser Des/PHY experience, and proficiency with Sigrity/HFSS/SIwave; IBIS-AMI simulations; lab instrumentation.
Join us at Cadence Design Systems as our next Senior Principal SI/PI Engineer — High-Speed IP Debug in San Jose, CA, United States.
The advertised compensation is 154..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior Principal SI/PI Engineer — High-Speed IP Debug role in the description above.
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