ASIC Packaging SI/PI Engineer - Hybrid; San Jose
Listed on 2026-10-13
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Engineering
Packaging Engineer, Systems Engineer, Electronics Engineer, Electrical Engineering
Cisco Silicon One is seeking a Signal and Power Integrity Engineer to develop next-generation ASIC packaging and verify SI/PI across interposer, substrate, and PCB. You will define design rules and collaborate with layouts and system partners to meet power, performance, and area targets.
The role requires strong background in high-speed signaling, SI/PI simulations, and post-layout extraction. You will work on high-volume packaging and contribute to cross-disciplinary efforts in a fast-paced
The following opportunity is for a ASIC Packaging SI/PI Engineer
- Hybrid (San Jose) with Cisco.
We are seeking a motivated ASIC Packaging SI/PI Engineer
- Hybrid (San Jose) to join Cisco in San Jose, CA, United States.
Consider building your career as a ASIC Packaging SI/PI Engineer
- Hybrid (San Jose) at Cisco.
The ASIC Packaging SI/PI Engineer
- Hybrid (San Jose) position in the Engineering field is open for applications.
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