Memory Interface Validation Lead; DDR
Listed on 2026-10-15
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Engineering
Validation Engineer
Rambus seeks a Validation Manager for its Memory Interface Chip unit to lead validation and characterization of memory buffer chips, leveraging DDR4/DDR5 expertise and strong Python automation. You will guide cross-functional teams, drive validation methodologies, and ensure high-quality silicon products.
The role combines hands-on bench work with process leadership in a dynamic, innovation-focused environment.
We invite applications for the Memory Interface Validation Lead (DDR4/5) position located in San Jose, CA, United States.
The advertised compensation is 162..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Memory Interface Validation Lead (DDR4/5) role in the description above.
We appreciate your interest in this position.
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