Packaging Engineering Director: -Speed Interconnects

SiMa.ai is seeking a Technical Director of Packaging Engineering in San Jose, CA to drive high‑performance FCBGA and SiP packaging from definition to mass production. This hands‑on leadership role requires owning SI/PI for LPDDR5x/6, PCIe Gen5, and related interfaces, while coordinating OSAT and substrate suppliers and leading a small, high‑impact team.

You will work closely with Design, Hardware and QA teams, ensuring robust thermo‑mechanical, reliability, and cost constraints are met, with

We are currently recruiting a Packaging Engineering Director:
High-Speed Interconnects for our team in San Jose, CA, United States.

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This posting is for the Packaging Engineering Director:
High-Speed Interconnects role , based in San Jose, CA, United States.

We are looking to fill the Packaging Engineering Director:
High-Speed Interconnects position  in San Jose, CA, United States.