ASIC Failure Analysis Engineer; Hybrid

The application window is expected to close on: 11/05/2026 This is a hybrid position with approximately 3+ days in office in San Jose, California, United States.

As a Failure Analysis Engineer, you will be part of the Quality and Reliability group, performing failure analysis of ASIC products. Should have a passion for problem solving and a strong technical background in semiconductor failure analysis techniques and root cause analysis.

This role will require high level of collaboration and interaction with Product Test Engineering, Design Engineering, Quality Engineering, Assembly Engineering and Foundry Engineering teams. The successful candidate must be able to work well within a team and have excellent communication and organizational skills with customers and vendors. Experience with a variety of semiconductor failure analysis techniques and test equipment is required, along with the ability to interpret results and provide clear guidance on causes of failure.

• Conduct root cause failure analysis of silicon product reliability test and field failures and propose corrective actions.
• Develop and implement standard processes for failure analysis using all types of FA equipment.
• Coordinate all the logistics and instructions to direct the failure analysis process and carry out FA function in a systematic way.
• Document and report failure analysis results to management.
• Function as a technical resource for failure analysis questions.
• Develop and maintain relationships with FA service and equipment vendors.
• Interface with product, test, and design engineering groups to identify and characterize faults on emerging technologies, while providing fault isolation, identification, and characterization for yield/reliability failures.

• Bachelor's degree in Electrical/Electronics Engineering or related required.
• Master's degree preferred.
• 8+ years of experience in semiconductor failure analysis field.
• Previous background writing and executing FA plans and interpret results from FA techniques such as cross section, X-ray, CSAM, TDR, FIB, SEM, and TEM, IR/EMMI/OBIRCH.
• Validated ability to specify hardware and implement set up for dynamic FA using SIL (Solid Immersion Lens) and LSM (Laser Scanning Microscopy).
• Prior experience of fault isolation techniques using ATE, Scan/ATPG, MBIST to identify, isolate and characterize device-level faults.

• Semiconductor technology and process knowledge (Fab, Assembly, and Advanced Packaging).
• Good understanding of transistor function/basic electronics, semiconductor device physics and behavior under various operating conditions.
• Proficient in ATE docked dynamic fault isolation using LVP, LVI/SMI, LADA, TIVA techniques.
• Knowledge of JEDEC IC Qualification tests and requirements is beneficial.
• Applied experience driving physical failure analysis with suppliers.
• siops

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions.

Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.