ASIC DFT Engineer – Test & Post‑Silicon Validation
Listed on 2026-10-15
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Engineering
Test Engineer, Hardware Engineer, Electronics Engineer, Quality Engineering
Cisco's Silicon One team is seeking an ASIC Engineer focused on Design-for-Test. You will collaborate with Front-end RTL and backend physical design to drive DFT requirements early in the design cycle as we craft next-generation networking chips.
The role emphasizes post-silicon validation, ATE patterns, and verifying testability across the Implementation flow, with opportunities to influence DFT strategies and quality processes.
Step into the ASIC DFT Engineer – Test & Post‑Silicon Validation role at Cisco in San Jose, CA, United States and grow with us.
Learn more about the ASIC DFT Engineer – Test & Post‑Silicon Validation role in the description above.
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