DFT​/ATPG design Engineer

L&T is looking for experienced DFT Engineers with 5–10 years of semiconductor industry experience to support DFT implementation, verification, ATPG, MBIST, scan, and related test methodologies.

Develop, implement, and verify Design-for-Test (DFT) features for complex digital/SoC designs.

Work on scan insertion, scan architecture, ATPG pattern generation, analysis, and debug
.

Verify DFT features including Boundary Scan/JTAG, Scan, MBIST, and High-Speed test methodologies
.

Perform ATPG pattern generation, simulation, coverage analysis, and pattern debug
.

Work with MBIST architectures
, memory test methodologies, diagnostics, and failure analysis.

Work on IO test methodologies for interface and pin-level validation.

Support clock DFT and clock verification activities.

Analyze and resolve DFT-related issues at the RTL, gate-level, and ATPG stages.

Collaborate with RTL, Design Verification, Physical Design, STA, and Silicon Validation teams.

Use industry-standard DFT/ATPG EDA tools
, preferably the Siemens DFT suite
.

Participate in DFT verification, debug, coverage improvement, and test-quality activities.

5–10 years of relevant DFT/Design-for-Test semiconductor experience

Strong understanding of:

• Controllability & Observability
• Scan-based testing
• ATPG
• Scan insertion
• MBIST
• JTAG / Boundary Scan
• IO testing
• Clock DFT
• Hands-on experience with ATPG pattern generation, analysis, and debug
• Experience with MBIST implementation/verification and diagnostics
• Experience with DFT verification
• Experience with industry-standard DFT/ATPG EDA tools
• Familiarity with Siemens DFT tools strongly preferred
• Strong analytical and problem-solving skills
• Ability to work in a fast-paced semiconductor development environment