Formal Verification Methodology Lead
Listed on 2026-10-16
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Engineering
Test Engineer, Quality Engineering
Technical-Link N. America is seeking a senior Formal Verification engineer in San Jose to lead verification efforts and define scalable methodologies across IP, subsystems, and SoCs.
You will collaborate with Architecture and Design to drive formal-driven specs and implementations, and mentor teams in verification techniques. Ideal candidates have 5+ years in formal verification, System Verilog/SVA fluency, and experience with Jasper Gold or VC-Formal.
We are seeking a motivated Formal Verification Methodology Lead to join Technical-Link N. America in San Jose, CA, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Formal Verification Methodology Lead role in the description above.
We appreciate your interest in this position.
Join Technical-Link N. America and contribute to our ongoing work.
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