Principal Micro-architect, Coherent Interconnect

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world.

Come build with us!

As a Principal Micro-architect, you will lead the microarchitecture development of custom coherent interconnect IP and/or last-level cache (LLC) blocks for next-generation designs. In this role, you will drive key aspects of coherent interconnect RTL design, including performance and power optimization, logic debug, and timing closure. Success in this role requires a strong foundation in computer architecture, microarchitecture, and RTL design.

• Own the development and delivery of custom coherent interconnect IP and/or LLC blocks, ensuring high-quality execution and timely project completion.
• Collaborate closely with system architects to define and develop next-generation coherent interconnect and LLC architectures.
• Drive microarchitecture definition and specification, from early architectural exploration and microarchitectural research through detailed specification development and refinement.
• Partner with verification teams to ensure functional correctness and robust validation of the design.
• Develop high-quality RTL implementations that meet performance, power, and area (PPA) goals.
• Work with performance and power teams to optimize architecture and RTL implementations for efficiency and scalability.
• Collaborate with physical design and CAD teams to resolve implementation, timing, and integration challenges.
• Provide technical leadership and mentorship to junior engineers across the team.

• 15+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master's degree, or 11+ years of experience with a PhD
• Strong background driving RTL design of coherent interconnect and LLC sub-blocks for high-performance digital designs
• Demonstrated experience spanning architecture definition through RTL implementation
• Familiarity with on-chip network topologies such as mesh, ring, and crossbar interconnects, along with working knowledge of Arm AMBA5 CHI, AMBA4 ACE, AXI, and related coherent interconnect protocols.
• Deep expertise in Verilog/System Verilog and solid understanding of the complete ASIC design flow including STA, DFT, ECO flows, etc.
• Strong understanding of memory subsystem architecture, coherent cache design, system caches, coherency mechanisms, and directory-based snoop filter protocols.
• Proven experience leading technical initiatives, mentoring engineers, and collaborating effectively across dynamic, geographically distributed teams with strong communication and interpersonal skills.
• Experience with a scripting language like Perl or Python is a plus

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented…