Senior Verification Engineer - SystemVerilog/UVM, Equity
Listed on 2026-10-16
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Engineering
Test Engineer
Broadcom is seeking qualified individuals to join a high-performance design team working on SoC and IP development. You will contribute to state-of-the-art subsystem verification, collaborating with design and verification teams to meet customer requirements in a fast-paced environment.
The candidate should have extensive System Verilog/UVM experience, strong debugging skills, and excellent communication. A Bachelor's degree in EE/CS or equivalent is required, with 8+ years in industry and legal
Consider building your career as a Senior Verification Engineer
- System Verilog/UVM, Equity at Broadcom.
We invite applications for the Senior Verification Engineer
- System Verilog/UVM, Equity position located in San Jose, CA, United States.
The following role is for a Senior Verification Engineer
- System Verilog/UVM, Equity with Broadcom.
Our team is growing, and we are hiring a Senior Verification Engineer
- System Verilog/UVM, Equity in San Jose, CA, United States.
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