Lead ASIC DFT & DV Engineer
Listed on 2026-10-17
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Engineering
Test Engineer, Hardware Engineer
Cisco Systems, Inc. in San Jose, CA is seeking a DFT Verification Lead within the Silicon One team. This hybrid role requires three days per week on-site at Cisco's San Jose location and involves test planning, test bench development, and DFT architecture to support ATE screening and in-system test.
You will collaborate with Front-end RTL and backend PD teams, driving high-quality DFT verification and debugging with minimal mentorship. Strong System Verilog and scripting skills are essential.
Consider building your career as a Lead ASIC DFT & DV Engineer at Cisco Systems, Inc.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Lead ASIC DFT & DV Engineer role in the description above.
We appreciate your interest in this position.
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