Senior ASIC Packaging SI/PI Engineer; Hybrid
Listed on 2026-10-17
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Engineering
Systems Engineer, Packaging Engineer, Electronics Engineer, Electrical Engineering
Cisco Silicon One is seeking a Signal and Power Integrity Engineer to join their ASIC team in San Jose, CA. This hybrid role involves developing and verifying packaging for high-performance silicon devices used in data networks.
The ideal candidate has a strong background in high-speed signaling, SI/PI simulations, and experience with Cadence Sigrity, Ansys HFSS, and EM flows. Responsibilities include design rules for ultra-high-speed signaling and post-layout extraction.
We invite applications for the Senior ASIC Packaging SI/PI Engineer (Hybrid) position located in San Jose, CA, United States.
This posting is for the Senior ASIC Packaging SI/PI Engineer (Hybrid) role at Anysilicon, based in San Jose, CA, United States.
We are looking to fill the Senior ASIC Packaging SI/PI Engineer (Hybrid) position at Anysilicon in San Jose, CA, United States.
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