Senior -Chip Physical Verification Engineer
Listed on 2026-10-17
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Engineering
Test Engineer, Electronics Engineer, Systems Engineer, Quality Engineering
Broadcom is seeking a senior ASIC verification engineer to join its sign-off flows team in San Jose. You will focus on physical verification, ESD checking, and package RDL routing, driving LVS/DRC/ANT/ERC checks and rule-deck debugging.
The role requires extensive full-chip verification experience and strong scripting skills with Perl, Tcl, or C shell to automate flows and debug issues across Cadence and Synopsys tools.
The Senior Full-Chip Physical Verification Engineer role at Anysilicon is now open for applications in San Jose, CA, United States.
Please review the full job details above before applying.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in San Jose, CA, United States.
This opportunity is part of our work in Engineering.
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