Junior ASIC Design Engineer - Verilog & Debug

Cisco's Silicon One team is seeking an ASIC Design Engineer intern to help design and integrate next-generation silicon for core networking products. You will work with cross-functional teams across design, verification, and physical design to ensure high-performance, power-efficient solutions.

You will gain hands-on experience in Verilog/System Verilog, RTL implementation, timing analysis, and full-chip bring-up, while contributing to post-silicon validation and debugging efforts.

For the Junior ASIC Design Engineer
- Verilog & Debug position at Cisco, we are reviewing applications now.

Join us at Cisco as our next Junior ASIC Design Engineer
- Verilog & Debug in San Jose, CA, United States.

We are currently recruiting a Junior ASIC Design Engineer
- Verilog & Debug for our team in San Jose, CA, United States.

This is a strong opportunity to take on the Junior ASIC Design Engineer
- Verilog & Debug role at Cisco.