ASIC Design Verification Emulation Engineer

Join Cisco's Silicon One team in San Jose, CA, where you will play a pivotal role in developing a unified silicon architecture for web-scale and service provider networks. This position offers a unique blend of resources from a large organization and the dynamic culture of a smaller team, providing ample growth opportunities.

Responsibilities:

• Set vision and strategy for ASIC verification methodology and execution across multiple programs and product lines.
• Serve as technical authority and mentor for verification teams, fostering technical excellence and innovation.
• Lead architecture and implementation of scalable, reusable verification infrastructure and methodologies.
• Drive cross-functional initiatives to improve verification efficiency, quality, and coverage at scale.
• Influence ASIC architecture and design to enable robust verification and high-quality silicon.
• Serve as subject matter expert and advisor on industry trends, best practices, and new technologies.
• Provide technical leadership in root cause analysis and resolution of complex issues during bring-up and post-silicon validation.

Qualifications:

• Bachelor's degree with 7 years of related experience, or Master's degree with 4 years of related experience, or PhD with 1 year of related experience.
• Experience in System Verilog, UVM, and verification methodologies including emulation.
• Experience architecting verification strategies for complex ASIC programs.
• Experience leading verification teams or projects.
• Experience in scripting (Python, Perl) and C/C++ programming language.

Skills:

• Strong leadership, communication, and mentoring skills.
• Deep expertise in multiple protocols and large-scale SoC architectures.
• Experience with advanced emulation, prototyping, and formal verification tools at scale.
• Experience with silicon bring-up and post-silicon debug.