Senior Emulation Architect - Pre-Silicon Validation
Listed on 2026-10-17
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Engineering
Systems Engineer, Test Engineer, Validation Engineer
Astera Labs in San Jose, CA seeks a Principal Emulation Engineer to build and operate emulation environments for stress-testing complex ASICs and SoCs prior to silicon. You will lead cross-functional verification with design, firmware and systems teams, and validate PCI Express, CXL, Ethernet, DDR, NVMe and related interfaces across pre-silicon validation, with hands-on debugging and technical leadership.
You will contribute to a robust verification strategy, scale-up emulation workflows, and
As a Senior Emulation Architect
- Pre-Silicon Validation, you will play an important part at Astera Labs in San Jose, CA, United States.
We would love to welcome a new Senior Emulation Architect
- Pre-Silicon Validation to our organisation in San Jose, CA, United States.
For the Senior Emulation Architect
- Pre-Silicon Validation position at Astera Labs, we are reviewing applications now.
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