ASIC DFT Engineer Gen Networking Chips
Listed on 2026-10-17
-
Engineering
Electronics Engineer, Systems Engineer, Hardware Engineer, Test Engineer
Cisco Systems, Inc. is seeking an ASIC Engineer with a primary focus on Design-for-Test (DFT).
You will collaborate with Front-end RTL and backend physical design teams to drive DFT requirements early in the design cycle and contribute to next-generation networking chips. You will help lead the DFT and quality processes through implementation and post-silicon validation, with exposure to PD sign-off activities.
Join us at Cisco Systems, Inc as our next ASIC DFT Engineer – Next-Gen Networking Chips in San Jose, CA, United States.
All applications are reviewed carefully by our team.
The position is based in San Jose, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 155..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).