Senior SystemVerilog RTL Design Engineer, 5nm Equity

Broadcom is seeking a senior System Verilog RTL engineer in San Jose, CA to drive designs from specification through timing closure and physical hand-off. You will work with Architecture, Verification, and Physical Design to mitigate risks and ensure milestones are met, applying advanced RTL techniques for 5nm and below processes.

The role requires a strong background in System Verilog, PPA optimization, CDC/RDC analysis, and low-power design.

This posting is for the Senior System Verilog RTL Design Engineer, 5nm+ | Equity role at Broadcom, based in San Jose, CA, United States.

Join us at Broadcom as our next Senior System Verilog RTL Design Engineer, 5nm+ | Equity in San Jose, CA, United States.

We are currently recruiting a Senior System Verilog RTL Design Engineer, 5nm+ | Equity for our team in San Jose, CA, United States.