Senior ASIC DFT Emulation Lead
Listed on 2026-10-18
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Engineering
Hardware Engineer, Test Engineer
Cisco Systems in San Jose, CA is seeking an ASIC DFT - Emulation Technical Lead to architect state‑of‑the‑art emulation environments and drive pre‑silicon testing for the Silicon One family.
You will collaborate with front‑end RTL, physical design, and ATPG teams to troubleshoot issues, validate MBIST, JTAG, and scan architectures, and ensure high‑quality post‑silicon pattern conversion for next‑generation hardware platforms.
We are looking to fill the Senior ASIC DFT Emulation Lead position at Cisco Systems in San Jose, CA, United States.
We have an opening for a Senior ASIC DFT Emulation Lead in San Jose, CA, United States within Engineering.
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