ASIC Design Verification Engineer

This is an onsite role based in San Jose, CA.

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly.

Join us to power the future of the digital world.

As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You’ll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco’s hardware platforms. You will:

• Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure.
• Build DV environments from scratch for block and cluster levels.
• Develop, implement, and enhance test plans and tests for block and cluster verification, using both constraint-random and directed stimulus.
• Ensure comprehensive verification coverage through code and functional coverage implementation and review.
• Qualify RTL design by running Gate Level Simulations on netlists.
• Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration.
• Support design testing in emulation environments.

• Bachelors degree in Computer, Electrical or Electronics Engineering,+ 5 years of relevant technical experience, or Masters degree in a related field + 3 years of relevant technical experience, focused on ASIC design and verification.
• Experience in System Verilog or UVM methodology.
• Experience building reusable and scalable test benches from scratch.
• Experience with scripting using Perl and/or Python.

• Experience with forwarding logic, parsers, or P4.
• Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
• Knowledge of formal verification tools (e.g., IEV or VC Formal).
• Domain knowledge in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions,…