Principal Physical Verification Engineer

San Jose, CA

Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation of the industry's first 2nm coherent DSP silicon. Bloomberg also reported that Alphabet's CapitalG has backed Celero at a $3B valuation. As we continue to grow, we're hiring exceptional talent across the United States, Canada, and Argentina for a variety of exciting opportunities.

We are seeking a Full-Chip Physical Verification Engineer to join our Physical Design team and help deliver complex digital blocks and full-chip implementations in advanced process technologies. This role will own all aspects of Physical Verification execution on advanced TSMC nodes, ensuring design quality, manufacturability, and tapeout readiness. The ideal candidate has successfully completed multiple tapeouts and brings deep expertise in physical verification methodologies, including driving improvements in quality, execution efficiency, and predictable delivery across multiple programs.

You will work closely with the Analog Design and Physical Design teams to identify and resolve verification challenges while ensuring designs meet aggressive performance, manufacturability, and schedule objectives.

Team & Project Leadership

• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks

• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules

• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews

• Bachelor's or Master's degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications

• Physical Verification tools (Synopsys IC Validator (ICV), Siemens Calibre)
• Able to assemble a flow to support block/chip level PV

• Floor planning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration

• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)

For government reporting purposes, we ask candidates to respond to the below self-identification survey.

Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiring process or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Celero Communications, Inc.’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.

As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measure the effectiveness of the outreach and positive recruitment efforts we…