Principal Design Engineer Posted

## Principal Design Engineer San Jose, California, United States of America Apply Now Find out how well you match with this jobJob :
JR104722
** Our vision is to transform how the world uses information to enrich life for
* all*.
** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
** Department Overview
** The Non-Volatile Engineering Group (NVEG) at Micron develops memory products that are best-in-class in die size, performance, reliability, and power! Our mission is to innovate and deliver groundbreaking non-volatile memory solutions such as NAND. As the pace of technology accelerates, NVEG is aggressively embedding AI across every stage of the design flow — from circuit exploration and layout optimization to silicon debug and specification analysis — and we are looking for engineers who not only use AI in their daily work but also actively reshape our engineering workflows to unlock AI’s full potential!

** Position Overview
** As a Principal Design Engineer in NVEG, you will architect, design and sign off the high-speed IO interface of next-generation NAND flash, moving data between the NAND die and the host controller at multi-GT/s rates under tight power, area and signal-integrity limits. You will own IO blocks end to end, from spec and architecture through circuit design, layout guidance, verification and silicon correlation.

You will set IO architecture direction across products, lead task forces, and make the key trade-offs that hit aggressive data-rate and power targets. AI is a central pillar of how this team works: you will use AI tools daily and reshape workflows to continuously improve design efficiency in time and effort.

** Responsibilities*
* * IO architecture & ownership:
Define, design and verify major IO blocks(output driver, pre-driver, serializer, slew-rate control, equalizers, input receiver, Vref generator, deserializer, clock distribution, multi-phase clock generation, DCC/QEC, calibration & training circuits) to meet ONFI/JEDEC timing and electrical specs
* Timing & signal integrity:
Lead the IO timing budget (tDIVW, tDVW, setup/hold, jitter, duty-cycle distortion). Work with SI/PI engineers on channel, package and power-delivery effects (ISI, crosstalk, SSO noise, VCCQ ripple) and follow through between channel simulation and circuit design.
* Power, area & physical design:
Optimize IO power (ICCQ, energy per bit) and area. Drive floorplan, pad-ring and bump planning, clock routing and shielding with layout, and correlate post-layout results.
* Robustness & reliability:
Design for PVT, mismatch (Monte Carlo/high-sigma), aging (NBTI/HCI), ESD/latch-up and multi-die loading, with trims and margins that hold across the product lifetime.
* Silicon validation & debug:
Plan characterization with product and test engineering, lead failure analysis of IO timing and electrical fails, and feed lessons back into the next design.
* Specs & customers:
Work with Applications Engineering and system teams to evaluate new interface specs and customer requests, and quantify feasibility and design trade-offs.
* Build efficiency by using AI daily. Incorporate AI into your work and adjust workflows. Summarize data from PVT, Monte Carlo, and post-layout SIM. Compose and maintain block-level and sub-system documentation to improve design efficiency continuously.
* Build agents, prompt libraries and scripts for recurring IO tasks, and restructure simulation setups and review checklists so AI can work on them.
* Pilot new tools and models, publish standard methodologies, and supervise measurable cycle-time and quality gains.
* Technical leadership & mentorship:
Present to design reviews and expert panels, and mentor engineers on IO fundamentals and AI-first ways of working.  
** Minimum Qualifications*
* * BS/MS/PhD in Electrical Engineering or a related field with 12+ years of high-speed IO or mixed-signal IC design experience, including leading IO architecture on multiple products.
* Deep expertise in high-speed transmitter and receiver design (drivers, receivers, serializer/deserializer, equalization) and source-synchronous timing. Strong background in clocking for IO: multi-phase clock generation, DCC/QEC, delay lines, and jitter and duty-cycle analysis.
* Experience closing IO timing and electrical specs across PVT, mismatch and aging, including impedance…