Front-End ASIC Design Engineer — RTL & Verification; Equity
Listed on 2026-10-18
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Engineering
Electronics Engineer, Hardware Engineer, Test Engineer
Credo is seeking a Digital Design Engineer to drive front-end ASIC design, verification of complex logic blocks, and collaboration with Physical Design teams toward successful tape-outs. A base salary range of $80,000–$133,000 is offered, with discretionary bonus, equity, and comprehensive benefits.
The role requires at least a Bachelor’s in Electrical/Electronic or Computer Engineering with 2–7 years (or a Master’s with up to 5 years) of related experience.
Join us at Credo as our next Front-End ASIC Design Engineer — RTL & Verification (Equity) in San Jose, CA, United States.
We are currently recruiting a Front-End ASIC Design Engineer — RTL & Verification (Equity) for our team in San Jose, CA, United States.
This is an excellent opportunity to take on the Front-End ASIC Design Engineer — RTL & Verification (Equity) role at Credo.
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