Senior FPGA Timing Engineer – STA & Closure Lead
Listed on 2026-10-18
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Engineering
Electronics Engineer, Systems Engineer, Automation & Mechatronics Engineer, Hardware Engineer
Altera Corporation in San Jose, California, is seeking a Timing Engineer to lead timing activities across a subsystem, partnering with Design, Architecture and Physical Design to achieve timing convergence from implementation to sign-off.
The role requires strong STA, timing constraints, and advanced sign-off methods, with experience on modern process nodes; you will drive timing budgets, clock planning, and ECOs, and collaborate with RTL, PD and full-chip teams.
This role, Senior FPGA Timing Engineer – STA & Closure Lead at Altera Corporation, could be your next opportunity.
This opportunity is part of our work in Engineering.
The advertised compensation is 119..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior FPGA Timing Engineer – STA & Closure Lead role in the description above.
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